The present invention relates to a memory device, and, more particularly, to a refresh technique for use in the memory device.
As well-known in the art, a memory device employs a capacitor as a unit element for data storage and a transistor for its access, wherein the capacitor refers to a cell. In the memory device, data is written by applying a high electric potential to the cell when data of ‘1’ is stored therein, and by applying a low electric potential to the cell when data of ‘0’ is stored therein. The capacitor constituting the cell is designed in a manner that an electric charge therein should be always maintained as long as there is no change of an electric potential of the connection terminals of the capacitor if it is ideal. In fact, however, the capacitor loses the electric charge stored therein in the form of a leakage current with the passage of time, which makes it impossible to identify whether the written data is ‘1’ or ‘0’. Therefore, it is necessary to perform a series of processes that periodically senses data stored in each cell and again stores it therein in order to continuously maintain data. This series of processes is called a refresh operation.
FIG. 1 is a diagram showing a structure of a conventional circuit which generates a refresh signal.
A refresh signal AFACT refers to a signal for generating a refresh command RE. As shown in the drawing, this signal is generated by logically combining a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE. Specifically, when these signals are inputted from outside, they are in the form of inverted signals, in which the subscript ‘b’ is added to each input pad to indicate the state, as shown in the drawing.
The refresh signal AFACT is generated when the chip select signal CS is a logic high, the row address strobe signal RAS is a logic high, the column address strobe signal CAS is a logic high, and the write enable signal WE is a logic low. That is, the refresh signal AFACT of a logic high is generated to an output terminal when a logic low is applied to a CSb terminal, a logic low to a RASb terminal, a logic low to a CASb terminal, and a logic high to a WEb terminal.
FIG. 2 is a diagram showing a structure of a conventional circuit which generates a refresh command.
The circuit as shown in FIG. 2 serves to generate a refresh command RE by using the refresh signal AFACT. In other words, the refresh command RE is generated by adjusting the width of the signal by a NAND gate and a driver (inverter) by using the refresh signal AFACT and its delayed signal through a delay circuit.
FIGS. 3 and 4 are diagrams for explaining a refresh operation, wherein FIG. 3 is a diagram showing the structure of a bit line sense amp and its peripheral circuits and FIG. 4 is a diagram in which the refresh operation period is divided into an active interval and a precharge interval that are arranged in the sequence of time.
Referring to FIG. 3, a word line WL is enabled in response to an active command and cell data is carried on a positive bit line BL. At this time, the positive bit line BL and a negative bit line BLb have a potential difference of dV. When the bit line sense amp senses this difference, it makes the positive bit line BL have a core voltage VCORE and the negative bit line BLb have a ground voltage VSS. Following the active operation, the precharge operation allows the word line WL to be disabled, the cell voltage to be isolated, and the voltage levels of the positive bit line BL and the negative bit line BLb to be a bit line precharge voltage VBLP.
Referring to FIG. 4 in the order of time, after the bit lines BL and BLb pair has been equalized to the bit line precharge voltage VBLP, first, the bit line equalizing operation becomes deactivated (i.e., a bleq signal of FIG. 3 is a logic low). Second, the word line WL becomes activated and the cell data is carried on the bit line BL, and third, the sense amp driver becomes on and the bit line sense amp starts the sensing operation. After this active operation has been completed, if the operation goes to the precharge interval, fourth the word line WL becomes deactivated. Fifth, the sense amp driver becomes off and the operation of the bit line sense amp is stopped, and finally, the positive bit line BL and the negative bit line BLb are equalized to the level of the bit line precharge voltage VBLP.
The conventional memory device stabilizes the bit line precharge voltage VBLP and a cell plate voltage VCP to ½ of the core voltage VCORE by using the refresh command during an initialization process in which the memory device normally operates after its power-up.
FIG. 5 is a timing chart showing an initialization process of a DDR3 (double data rate3) memory device.
As shown in FIG. 5, in case of the DDR3 memory device, there exists no separate refresh command in the initialization process, and after its reset, a clock enable signal CKE (which is a signal for synchronizing the memory device with a clock) becomes a logic high level and thereafter a MRS (mode register set) command is performed. As such, if there is no separate refresh command in the initialization process, the bit line precharge voltage VBLP and the cell plate voltage VCP may have a certain level other than ½ level of the core voltage VCORE after the initialization process.
FIG. 6 shows levels of the bit line precharge voltage and the cell plate voltage when the refresh operation is not performed.
As shown in the drawing, if there is no separate refresh command in the initialization process, the level of the bit line precharge voltage VBLP may not reach ½ of the core voltage VCORE. And the cell plate voltage VCP may have a level of ½ core voltage VCORE±dV. If the bit line precharge voltage VBLP and the cell plate voltage VCP are unstable, a failure may occur during the operation of the memory device after the initialization.